1. Field of the Invention
The present invention relates to a clock switching circuit for selecting and outputting one clock signal from a plurality of multiphase input clock signals.
2. Description of the Related Art
In many circuits for processing signals in a communication system, reproducing data for a recording medium and controlling servo operation thereof, a plurality of clock signals of an identical frequency in different phases (multiphase clock signals) are used for the purpose of over-sampling of data or the like. In these circuits, a clock switching circuit is often provided, which selects a desired clock signal from the multiphase clock signals by switching the multiphase clock signals. For example, U.S. Pat. No. 6,307,403, which is hereby incorporated by reference, discloses selectors that select one clock signal from multiphase signals.
FIG. 1 is a diagram illustrating an 8-input/1-output clock switching circuit of the related art. In FIG. 1, a clock switching circuit 80 for switching 8-phase input clock signals ICLK1 to ICLK8 is illustrated. The clock switching circuit 80 includes 8-input/1-output selectors 81 and 82, flip-flop circuits 83 to 85 for controlling the selector 82, and an AND gate 86 for providing latch timing to the flip-flop circuits 83 to 85.
As shown in FIG. 1, the clock switching circuit 80 receives the 8-phase input clock signals ICLK1 to ICLK8, selects only one of the 8-phase input clock signals ICLK1 to ICLK8 and outputs the selected one clock signal as OCLK, in accordance with a control signal ICODE[2:0] consisting of selection signals ICODE[0] to ICODE[2] of three (3) bits. The 8-phase input clock signals ICLK1 to ICLK8 are provided to both of the selectors 81 and 82, while each of the selection signals ICODE[0] to ICODE[2] is provided to a data input terminal of each of the corresponding flip-flop circuits 83 to 85. The control signal ICODE[2:0] is also provided to a control terminal of the selector 81, and this signal controls switching operation of the selector 81. Output signals CLK1 from the selector 81 and OCLK from the selector 82 are provided to an AND gate 86, and a trigger signal CLK2 from the AND gate 86 is provided to each trigger input terminal of the flip-flop circuits 83 to 85. The flip-flop circuits 83 to 85 transfer the selection signals ICODE[0] to ICODE[2] to the selector 82 as transferred selection signals SOUT[0] to SOUT[2] respectively. The transferred selection signals SOUT[0] to SOUT[2] of three (3) bits from the flip-flop circuits 83 to 85 control switching operation of the selector 82. The selector 82 provides a selected output clock signal OCLK.
FIG. 2 is a waveform diagram of 8-phase input clock signals ICLK1 to ICLK8 that are provided to the clock switching circuit 80 of the related art of FIG. 1. As shown in FIG. 2, each of the 8-phase input clock signals ICLK1 to ICLK8 has a different phase, and the phases of each are sequentially advanced toward the ICLK8 from the ICLK1.
When a Gray code of three bits is adapted to the control signal ICODE[2:0] of FIG. 1, an input clock signal (e.g., ICLK3 or ICLK1 of FIG. 2) adjacent to the currently selected input clock signal (e.g., ICLK2 of FIG. 2) can be selected by increasing or decreasing the Gray code by a minimum value.
FIG. 3 is a timing chart of a clock switching operation in the clock switching circuit 80 of the related art of FIG. 1. FIG. 3 illustrates an example in which the selection of an input clock signal ICLK2 (shown in FIGS. 1 and 2) is switched to the selection of an input clock signal ICLK1 (shown in FIGS. 1 and 2), i.e., the selected output clock signal OCLK of FIG. 1 is switched from ICLK2 to ICLK1 during the period P between timings T82 and T83 of FIG. 3.
As shown in FIG. 3, when the control signal ICODE[2:0] is changed at timing T81, CLK1 (an output signal from the selector 81 of FIG. 1) immediately changes from being the same signal as ICLK2 (shown in FIG. 1) to being the same signal as ICLK1 (shown in FIG. 1), while OCLK (an output signal from the selector 82 of FIG. 1) remains the same signal as ICLK2 (shown in FIG. 1). Thereafter, at timing T82 of FIG. 3, which is at the beginning of a period P in which both the ICLK1 and ICLK2 are at a High Level, the trigger signal CLK2 (an output signal from the AND gate 86 of FIG. 1) changes from a Low level to a High level and triggers the flip-flop circuits 83 to 85 of FIG. 1. In response to the triggering, the selection signals ICODE[0] to ICODE[2] are transferred to the selector 82 of FIG. 1 as transferred selection signals SOUT[0] to SOUT[2]. Consequently, OCLK (an output signal from the selector 82 of FIG. 1) is switched so as to be the same signal as ICLK1 during the period P between timing T82 and T83 of FIG. 3.
In the timing chart of FIG. 3, there exists a glitch on CLK1 (an output signal from the selector 81 of FIG. 1) at the timing T81. The glitch appears in CLK1 because the control signal ICODE[2:0] is changed at the timing T81, which occurs right after the input clock signal ICLK2 falls to a Low level, but while the input clock signal ICLK1 remains at a High level. Such a glitch causes erroneous operation of the clock switching circuit 80 of FIG. 1.
FIG. 4 is another timing chart of clock switching operation in the clock switching circuit 80 of the related art of FIG. 1. In FIG. 4, similarly to in FIG. 3, a trigger signal CLK2 (an output signal from the AND gate 86 of FIG. 1) changes from a Low level to a High level at timing T92, which occurs at the beginning of a period P, in which ICLK1 and ICLK2 are at a High Level, triggering the flip-flop circuits 83 to 85 of FIG. 1.
However, in FIG. 4, the transferred control signal SOUT[2:0] (an output signal from the flip-flop circuits 83 to 85 of FIG. 1) does not change immediately after the change of CLK2 occurring near timing T92. The change of the transferred control signal SOUT[2:0] occurs at timing T94, which is after the period P. The delay in the change of the transferred control signal SOUT[2:0] is caused by delayed operation of the flip-flop circuits 83 to 85. Consequently, a glitch appears in the OCLK (an output signal from the selector 82 of FIG. 1) because the OCLK was switched from a level matching ICLK2 to a level matching ICLK1 at the timing T94, that is, after ICLK2 falls to a Low level at timing T93, but while ICLK1 remains at a High level. The glitch in OCLK (one of the input signals of the AND gate 86 of FIG. 1) produces another glitch in CLK2 (an output signal from the AND gate 86 of FIG. 1), too. These glitches cause erroneous operation of the clock switching circuit 80 of FIG. 1.
As described above, FIG. 4 shows an example of erroneous operation based on the delay operation of the flip-flop circuits 83 to 85 of FIG. 1. Similar erroneous operations of the clock switching circuit 80 of FIG. 1 may occur based on the delay operation of the selectors 81, 82 or AND gate 86 when the frequency of the multi-phase input clock signals (ICLK1 to ICLK8 of FIG. 1) becomes high. When the frequency of the multiphase input clock signals is high, the slight delay that occurs in operation of the flip-flop circuits 83 to 85, the selectors 81, 82 or AND gate 86 of FIG. 1 cannot be neglected, and the delay causes erroneous operations of the clock switching circuit 80 of FIG. 1.
Considering the problems described above, there remains an unmet need in the related art to provide a clock switching circuit having stable switching operation, especially when frequency of input of multiphase clock signals is high.